TSMC and National Yang Ming Chiao Tung University (NYCU) demonstrated a breakthrough in sub-1-nanometer transistor design by engineering a 0.42-nanometer-thick aluminum oxide layer at the interface between the channel material (molybdenum disulfide, MoS2) and the gate dielectric. This protects electron flow while maintaining extremely thin insulating layers, addressing a persistent barrier to 2D monolayer transistor performance.
The innovation bypasses traditional approaches focused on novel deposition or new dielectric materials. Instead, the researchers oxidized an ultrathin epitaxial aluminum layer deposited on the MoS2 surface, then added a high-κ hafnium oxide gate dielectric on top. The resulting structure delivers tighter electron-flow control and reduced resistance comparable to a 1-nanometer dielectric thickness— a significant achievement for atomically thin semiconductors that are only 0.7 nanometers thick.
Two-dimensional transistors enable greater gate control, lower resistance, and increased transistor density: future chips could reach 0.7-nanometer channel thickness and sub-3-nanometer channel length. The TSMC-NYCU work, published in Nature Electronics, provides a blueprint for scaling these structures and represents a major step toward the next generation of semiconductor devices beyond conventional silicon.