TSMC's A14 (1.4nm-class) process achieved close to 90% device performance and 90% 256Mb SRAM yield, announced during the company's earnings call on July 16, 2026. This marks a rapid 5% gain in device performance and nearly 10% improvement in SRAM yield since April 2026, when the process stood at >85% transistor performance and >80% SRAM yield. A14 is scheduled for mass production in 2H 2028, roughly 2.5 years away from announcement.
For context, N2 (TSMC's current-generation process) demonstrated >80% device performance and >50% SRAM yield in April 2023, then reached >90% device performance and >80% SRAM yield by April 2024. A14's maturation is significantly faster, partly due to TSMC's accumulated experience with second-generation gate-all-around nanosheet transistors built on lessons learned during N2's ramp. CEO C.C. Wei signaled that customer tape-out activity on A14 is already underway and ahead of schedule, spanning both smartphone and AI/HPC applications, suggesting near-term design commitments.
TSMC expects A14 to deliver 10–15% performance uplift at the same power versus N2, or 25–30% power reduction at the same frequency and complexity. Transistor density improvements are projected at 20% for mixed designs and 23% for logic. These gains position A14 as a competitive alternative to other advanced nodes in development across the industry.
For practitioners, A14's rapid progress means advanced-node capacity beyond N2 could come online ahead of industry consensus. Customers pre-staging designs signals confidence in yield maturity; early HVM is possible if device-level test data corroborates SRAM yield metrics. Watch for official customer announcements of A14 design wins to confirm demand beyond TSMC's internal roadmap.