Synopsys has launched a new Compute Express Link (CXL) 4.0 IP portfolio targeting one of AI infrastructure's most persistent bottlenecks: memory bandwidth and capacity. The portfolio includes a controller, IDE security module, silicon-proven physical layer, and verification IP, supporting CXL 4.0 alongside earlier generations (3.x, 2.0, 1.x) on a unified architecture. CXL 4.0, released in late 2025, doubles bandwidth to 128 GT/s, aligns with PCIe 7.0, and introduces port bundling that allows designers to combine multiple 16-lane links to exceed 2–4 TB/s of bandwidth per bundled port.
Memory capacity and bandwidth have been the binding constraint since at least 2012, according to Synopsys's Ron Loman. CXL is a cache-coherent interconnect built on PCIe's physical layer, enabling processors, accelerators, and memory devices to communicate and share resources at the system level. The new IP supports up to four retimers for signal reach at higher data rates, native x2 link widths, and a 256-byte latency-optimized flit to increase payload efficiency. Deployment of CXL 2.0 has reached volume production, while CXL 3.x (aligned with PCIe 6.0 and PAM4 signaling) is only beginning broader adoption; CXL 4.0 adoption is expected to accelerate as infrastructure designers chase disaggregated memory and compute across multi-die and rack-scale systems.
For architects, CXL 4.0 becomes a strategic enabler for AI inference at scale, complementing multi-die strategies and memory pooling that sidestep HBM supply constraints. The IDE security module with zero-cycle latency overhead and FIPS 140-3 readiness addresses growing needs in multi-tenant and confidential-compute environments. As hyperscalers increasingly pursue disaggregated compute (a progression Loman outlined from expansion to sharing to full disaggregation), mature CXL IP lowers implementation risk and accelerates time-to-silicon for custom AI accelerators and memory-intensive SoCs.