Samsung previewed next-generation memory architectures at FMS 2026 in Santa Clara, showcasing concept models zHBM and zNAND-O alongside the industry-first 400-plus-layer V10 BV-NAND. The company also began sampling HBM4E to customers in May following HBM4 mass production in February.
zHBM vertically stacks high-bandwidth memory directly above AI accelerators, shortening the physical distance data travels between compute and memory. Samsung claims a next-generation interface system incorporating zHBM will deliver approximately 8x the performance of HBM5 while achieving over 10x memory density, 3x better energy efficiency, and more than 50% lower thermal resistance compared to HBM5.
zNAND-O, also in development, combines storage and logic in four- and eight-layer configurations for edge AI applications requiring real-time, low-latency processing. V10 BV-NAND, the most concrete near-term product, uses wafer bonding to stack over 400 layers, delivering ~58% higher density than the prior V9 generation while improving read, write, and I/O performance.
Samsung positioned itself as the only vertically integrated manufacturer spanning memory, foundry, and advanced packaging, enabling one-stop turnkey solutions for AI infrastructure. Architects tracking memory bottlenecks in large-scale training and inference should monitor zHBM's customer collaboration timeline and V10 BV-NAND's commercial availability, as both address the compute-memory distance problem at the core of next-gen accelerator design.