The Leti Innovation Days (LID World Summit 2026) in Grenoble (June 23–25) revealed a consensus among chip researchers, fab operators, and equipment makers: raw transistor performance is no longer the primary bottleneck for AI progress. Instead, architecture redesign—memory placement, power delivery, thermal management, photonics, and interconnect efficiency—will determine the next generation of GPU and accelerator systems.
CEA-Leti CEO Sébastien Dauvé framed the shift bluntly: 'Architecture, not raw compute' is AI's emerging constraint. Architects are redesigning entire systems to move data with less energy, deliver power more efficiently, and manage heat at scale. Key themes included back-end-integrated memories (filling gaps between SRAM and DRAM), 3D stacking and chiplet architectures placing memory closer to processors, silicon photonics for co-packaged optics and chiplet-level communication, and industrial-scale ramp of these technologies on 300-mm wafers. STMicroelectronics and partners presented their photonics platform at LID 26, signaling that photonic interconnects are moving inward from rack-level connections toward on-package and chiplet-level signal paths.
For chip architects and system designers, this signals a strategic pivot: monoolithic die shrinks alone will not unlock the next wave of AI capacity. System co-design, manufacturability, and industrial-scale integration of packaging, memory, and interconnect technologies are now competitive differentiators. Companies investing in 3D silicon stacking, advanced packaging, and photonics are positioning themselves to deliver the next inflection in AI compute efficiency; those betting solely on transistor density risk falling behind.