SK Hynix, TetraMem, and researchers from USC have jointly demonstrated a memristor-based in-memory computing (IMC) system-on-chip (SoC) optimized for edge AI inference. Fabricated on a 65-nanometer process and featuring 10 neural processing units (NPUs) with analog vector-matrix multiplication directly inside crossbar arrays, the chip delivers peak energy efficiency of 21.3 TOPS/W at 100 MHz—exceeding NVIDIA A100 INT8 efficiency by an order of magnitude on legacy process geometry. The design includes a custom depthwise-convolution (DWC) optimized NPU with zig-zag crossbar topology to accelerate lightweight models like MobileNetV1 with minimal power overhead.
Tested on the Visual Wake Words benchmark using a customized MobileNetV1Small network (36,000 parameters), the SoC achieved 80.36% end-to-end accuracy using low-precision (roughly 4-bit effective) quantized weights, demonstrating memristor feasibility for quantized inference. However, proof-of-concept limits loom: theoretical peak throughput (2.54 TOPS full-chip) falls 16x short of Microsoft Copilot+ requirements, and the test used only 5 of 10 standard NPUs, leaving total multi-NPU saturation unvalidated.
For practitioners: memristor-based IMC trades speed for extreme power efficiency on old nodes, suitable for always-on edge sensors and mobile talkback—not cloud inference. The 65nm fab story signals a strategy shift away from advanced node density toward analog-in-silicon performance per milliwatt. Watch whether SK's manufacturing depth (memristor integration on CMOS) enables volume production; if so, edge AI acceleration beyond GPU/NPU SLAs becomes viable for IoT and remote monitoring.