Imec roadmap targets 0.3nm by 2038; CFET transistors coming to A7 in 2033

Imec released its updated semiconductor process technology roadmap this week, charting a path to 0.3nm (3 ångström) node by 2038 while redefining Moore's Law away from pure dimensional scaling. The roadmap shows that conventional contact poly pitch (CPP) will stop shrinking at the A10 node in 2030 at 42nm, forcing chip makers to adopt new transistor architectures and 3D stacking to continue density gains.

The next major shift arrives at the A7 node (7 ångström, roughly 0.7nm) in 2033 with the introduction of Complementary FET (CFET) transistors, which stack n-type and p-type transistors vertically rather than placing them side by side. This 3D stacking removes the traditional n-p separation from standard cell height, enabling area reduction of up to 20% and extending scaling beyond the current Gate-All-Around (GAA) nanosheet generation.

Before CFETs arrive, forksheet transistors—an Imec invention—will bridge the gap from 2nm (A14) in 2028 through A10. Imec also positions High-NA EUV lithography (0.55–0.75 NA) as critical enabler for sub-ångström nodes, with Hyper-NA (0.75 NA) potentially supporting A2 and beyond. Beyond A3 in 2038, scaling will require sequential and bonded CFET structures plus 2D materials like transition metal dichalcogenides.

Architects tracking fab roadmaps should note that standard cell CPP remains flat from A10 through A5 (2035–2036)—classical Moore's Law has hit a wall. Future gains depend on heterogeneous 3D integration (CMOS 2.0), backside power delivery networks, and system-technology co-optimization that trades off node maturity by functional layer rather than scaling every functional block uniformly.